Most of the electronic circuits includes a bare-board and electronic devices. Generally the bare-board includes more than two layers and is fabricated by a printed circuit board (PCB) manufacturer. Many different devices are collected and assembled on that bare-board. Boolean logic circuits such as the AND, OR, NOT, NAND, NOR, XOR, NOR2 gates are well known and are used for implementing digital circuits in such as PCB logic.
U.S. Pat. No. 7,903,428 (Liu et al.) discloses an intra-connection layout for an array. An alterable area is disposed between the devices of a device array. The alterable area includes an insulation layer, a group of conductive wires and another group of conductive wires. The first conductive wires are disposed within the alterable area along a first direction for selectively connecting electrical paths in the first direction between different devices. The second conductive wires are disposed within the alterable area along a second direction for selectively connecting electrical paths in the second direction between different devices. The insulation layer is disposed within the alterable area and between the above-mentioned first conductive wires and second conductive wires, wherein the insulation layer has an opening to allow one of the first conductive wires and one of the second conductive wires to be contacted with each other.
U.S. Pat. No. 7,903,428 discloses openings 217, 218 in the insulation layer which are formulated according to the design of the circuit. Moreover, the second conductive wires are disposed over the insulation layer on previously exposed openings to comply with a specific design. It appears that the openings 217, 218 are made by cutting off parts of the previously disposed insulation layer. The conductive wires are printed with plurality of pads and the insulation bands are printed on the paths before the second conductive wires are printed.
In U.S. Pat. No. 7,903,428, the openings 217, 218 are formed in the insulation layer. It would be desirable to provide a matrix wherein there is no need to cut off openings in the insulation layer.